具電流誤差及突波雙重免疫之歸零技術以實現數位類比轉換器Digital to Analog Coverting method and converter insensitive to code-dependent distortions

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

14/025,435

專利證號

US 8,872,687 B2

專利獲證名稱

具電流誤差及突波雙重免疫之歸零技術以實現數位類比轉換器Digital to Analog Coverting method and converter insensitive to code-dependent distortions

專利所屬機關 (申請機關)

國立成功大學

獲證日期

2014/10/28

技術說明

此發明提出一個具電流誤差及突波雙重免疫之歸零技術(DEMDRZ)。在準位轉換的同時製造一個重置相位，故此準位轉換並不會與其前一個信號準位產生關聯性。DEMDRZ將匹配誤差量及瞬間切換突波造成的失真隨機分佈於雜訊平面上。其免除因訊號切換造成的突波問題，故本數位類比轉換架構不需採用溫度計編碼電路卻仍有極佳的 SFDR 性能。我們以40奈米 CMOS製程實現一個12位元操作於1.6 GS/s的DAC。量測結果顯示，在1.6 GS/s取樣下，整個Nyquist頻寬(<800MHz)皆可達到>70dB SFDR，而在2.8GS/s取樣下，皆可達到< -61dB的三階交互調變失真(IM3)。可分別滿足訊號產生儀器(signal generation instrumentation)及多載波頻率通訊系統(multi-carrier communication system)不斷提升的應用需求。再者，在單電源1.2V下僅消耗40毫瓦。晶片主動面積僅0.016平方毫米，小於一流文獻DAC所需面積的5%。據我們所知，我們以DEMDRZ所實現的DAC實現出全球最佳的性能指標。 This invention which we called DMRZ is proposed to implement a return-to-zero with mismatch and glitch insensitivity. The DMRZ provides a reset phase during the level transition; hence the level transition is independent of its previous output level. The DMRZ improves the SFDR by randomizing the mismatch- and transient-induced distortions over entire noise floor. The proposed DAC does not adopt any thermometer decoders and still exhibits good SFDR. A 12-bit compact, low-power, high-speed, DAC is implemented in TSMC 40nm CMOS process. The implemented DAC achieves >70 dB SFDR for signals over the 800 MHz Nyquist bandwidth at 1.6 GS/s and < -61 dB IM3 for signals over the 1.4 GHz Nyquist bandwidth at 2.8 GS/s. Further, it dissipates 40 mW with a single 1.2 V supply. The active area of the DAC is 0.016 mm2, which is less than 6% of other state-of-the-art 12-bit current steering DACs. Furthermore, the implemented DAC performs best with three common FoMs.

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