無參考訊號源時脈資料回復系統及其頻率偵測器

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

107141379

專利證號

I 681635

專利獲證名稱

無參考訊號源時脈資料回復系統及其頻率偵測器

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2020/01/01

技術說明

高速連結技術已普遍應用在消費電子產品，如 100 Gbps 乙太網路，USB 3.1 (10Gbps), PCIe 5.0 (32 Gbps), MIPI 3.0 (12 Gbps)等介面。高速信號在傳輸過程受到通道頻寬之非理想效應，將產生嚴重之符元干擾。在接收隨機信號時，時脈資料回復電路採用相位偵測器進行取樣時脈校正，其鎖頻範圍有限，因此需藉由鎖頻迴路予以協助。典型之鎖頻迴路可分為有參考信號源及無參考信號源兩種方式，前者可藉由鎖相迴路達到頻率預先追蹤，因此無頻率鎖定範圍之問題，缺點在於需額外之信號通道傳遞時脈，或使用外接之石英振盪器，提供參考信號。而後者多使用相位相關器(quadricorrelator) 進行頻率追蹤，然其頻率鎖定範圍有限，而在高通道損耗條件下，其無法正常工作。本專利提出新式之頻率追蹤暨時脈與資料回復電路，其可適用於高通道損耗下之資料傳輸，且無須參考信號源，具有其前瞻性及優越性。 High speed interfaces have been widely adopted in consumer electronics, including 100 Gbps Ethernet, USB 3.1 (10Gbps), PCIe 5.0 (32 Gbps), and MIPI 3.0 (12 Gbps), etc. Due to the limitation of channel bandwidth and non-idealities, the electrical signal may encounter severe inter-symbol interference (ISI) at the receiver side. To receive a pseudo random signal, a phase detector is commonly used in a CDR for timing adjustment, but its frequency acquisition range is limited and needs to collaborate with a frequency locked loop. Typically, the frequency locked loop can be categorized as a with reference or a referenceless architecture. The former one relies on a phase-locked loop for frequency acquisition, and is free from locking range issue. The demerits are that an extra channel is required for clock signal transmission, or an additional crystal oscillator is required. On the other hand, a typical referenceless frequency detector is based on a quadricorrelator architecture. But its locking range is still limited, which cannot function property when receiving a signal through a high loss channel. This patent proposes a new referenceless frequency detector, which can be utilized as an aid to the clock and data recovery circuit. It can be applied for data receiving over high loss channel, and outperforms the existing FD architectures.

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