具有能預測因製程與環境變異所造成時序錯誤的嵌入式脈衝時序電路系統PLUSE-BASED IN-SITU TIMING CIRCUIT SYSTEM WITH FUNCTION OF PREDICTIONG TIMING ERROR CAUSED FROM PROCESS AND ENVIRONMENT VARIATIONS

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

101145426

專利證號

I 489245

專利獲證名稱

具有能預測因製程與環境變異所造成時序錯誤的嵌入式脈衝時序電路系統PLUSE-BASED IN-SITU TIMING CIRCUIT SYSTEM WITH FUNCTION OF PREDICTIONG TIMING ERROR CAUSED FROM PROCESS AND ENVIRONMENT VARIATIONS

專利所屬機關 (申請機關)

國立成功大學

獲證日期

2015/06/21

技術說明

本發明係有關於一種具有能預測因製程與環境變異所造成時序錯誤的嵌入式脈衝時序電路系統，係包括有一由主儲存器及從屬儲存器構成之主從循序儲存器、一與主、從屬儲存器電連接路徑上一節點電連接之轉態偵測器，以及一電連接轉態偵測器之警告訊號產生器；其中，轉態偵測器將主儲存器之輸出延遲緩衝以形成一警告區域，並根據資料輸入的轉態以產生一對應脈衝寬度輸出，使得當資料輸入抵達警告區域時，警告訊號產生器可經由脈衝寬度和時脈輸入之邏輯動作產生一警告訊號；藉此，以預測靜態製程變異以及動態環境變異所造成的時序錯誤。 The invention relates to a pulse-based in-situ timing circuit system with a function of predicting timing error caused from PVT variations. It comprises a master-slave sequential storage which consists of a master storage and a slave storage, a transition detector electrically connected with a node on an electrical connection path of the master storage and the slave storage, and a first clock gate controller electrically connected to the transition detector, wherein the clock input of the system is delayed and buffered by the transition detector to form a warning zone. Furthermore, a corresponding pulse width output is generated according to the transition of the data input such that the first clock gate controller will generate a warning signal through the pulse width and logical action of clock input when data input reaches to the warning zone. Accordingly, the timing errors caused form the static process variation and dynamic environmental variation can be predicted.

備註

本部(收文號1090031211)同意該校109年5月29日成大技轉字第1095600304號函申請終止維護專利(成大)

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