換層佈線式差模蛇形延遲線結構

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

103112335

專利證號

I 477213

專利獲證名稱

換層佈線式差模蛇形延遲線結構

專利所屬機關 (申請機關)

中原大學

獲證日期

2015/03/11

技術說明

這專利提出一種共模雜訊抑制的新技術..就是用不同層的走線方式來降低弱偶和差模蛇形延遲微帶線..這用換層去取代傳統同層佈線的目的是要使這兩段線的延遲時間一致而來降低共模雜訊..這新的技術與傳統同一層佈線結構來比較..使得時域共模雜訊峰值可以抑制大於90%之多..且頻域部份的差模轉共模參數可以抑制大於20dB之多..而且意志的頻寬可以達非常寬頻的效果...這抑制的效能遠遠勝過之前的傳統佈線方式與其他抑制方法(強耦合轉角方式與接地防護線).. This pattern proposes a new common-mode noise reduction scheme that involves different-layers-routing turned traces to reduce the CMN in weakly coupled differential serpentine delay microstrip lines. The purpose of using different-layers-routing turned traces instead of same-layer-routing coupled turned traces (conventional scheme) is to cause the difference between the delay times of the two traces of the turn-traces section to approach zero to minimize the CMN. The proposed solution obtains a peak-to-peak amplitude of CMN in the time domain simulation that is more than 90% that obtained using the conventional scheme. The proposed reduction scheme in DSDMLs reduces the differential-to-common mode conversion by more than 20dB. The range of frequencies over which CMN is reduced is very wide, being almost the wide bandThe reduction using the proposed reduction scheme exceeds those achieved using previous reduction schemes, strongly coupled turned-traces and guard traces.

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