具有混合架構當作阻抗匹配之低雜訊放大器及其匹配方法LNA HAVING HYBRID STRUCTURE AND METHOD FOR IMPEDANCE MATCHING

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

102102904

專利證號

I 505632

專利獲證名稱

具有混合架構當作阻抗匹配之低雜訊放大器及其匹配方法LNA HAVING HYBRID STRUCTURE AND METHOD FOR IMPEDANCE MATCHING

專利所屬機關 (申請機關)

國立中興大學

獲證日期

2015/10/21

技術說明

本發明為一種具有混合架構當作輸入匹配之低雜訊放大器設計及輸入匹配方法。放大器包含電晶體、輸入匹配級、負載、輸出匹配級。以場效電晶體實現時，電晶體具有一閘極、一源極和一汲極；輸入匹配級則包括了一耦合結構及外接元件。輸入匹配級中之耦合結構由晶片內之金屬連接線構成，由輸入端接受一訊號連至偏壓端，再連結至電晶體的閘極形成子結構一；另外由電晶體源極至接地亦由晶片內之金屬連接線構成子結構二。子結構一與子結構二間具有磁性耦合。子結構一中的偏壓端可再接至外接元件如電感或傳輸線以提供直流偏壓並提供匹配之調整。 This technique is an impedance matching method for low-noise amplifier. The low-noise amplifier is compoesed of transisitors, input matching stage, load, and output matching stage. In CMOS process technology, the transistor has a gate terminal, a source terminal, and a drain terminal. The input matching stage in this proposed technique includes a coupling structure and an additional component. The coupling structure is formed by the interconnect metal in the chip. In the coupling structure, sub-structure A receives input signal and routes to bias terminal and then rountes to the gate terminal of the transistor; while the sub-structure B is also formed by interconnect metal that connect the source terminal of the transistor to the ground. There is magnetic coupling between sub-structures A and B. The bias terminal in structure A can be connect to an additional component (a inductor or a section of transmission line) for providing dc bias and tuning the input impedance.

備註

本會(收文號1120002852)同意該校112年1月9日興產字第1124300027號函申請終止維護專利(國立中興大學)

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