H.264視訊編碼技術

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

100120266

專利證號

I 524778

專利獲證名稱

H.264視訊編碼技術

專利所屬機關 (申請機關)

國立雲林科技大學

獲證日期

2016/03/01

技術說明

為了在影像壓縮上得到更好的壓縮率，在同一塊編碼區塊中，H.264/AVC中採用了各種不同大小的預測編碼模式(Coding Mode)去計算其對應的失真度(Distortion)及碼率(Bit Rate)的成本(Cost)，比較出最好的編碼模式，整個編碼上運算複雜度較其他影像壓縮規格高出很多。 為了加速H.264/AVC的硬體計算，本論文提出演算法來提早結束模式選擇的流程：分別是條件式省略INTRA編碼快速決策演算法及提前模式決策SKIP模式預測演算法。在參考軟體JM12.2的測試中，本論文較原架構節省了19% ~ 53% 的編碼時間，並且在編碼品質上只有些許可忽略的下降。 接著依上述快速演算法，用硬體描述語言將此演算法實現出即時VLSI晶片，我們提供3種不同時間長度結束一個MB的編碼，時間從17~802 cycles，合成面積為1893個Logic Element。 To improve the coding performance, H.264/AVC adopted 7 Inter modes, 13 Intra modes and 1 SKIP mode to reduce temporal or spatial redundancy. The best coding mode for one MB (macroblock) can be obtained by searching all possible modes and compared with the rate-distortion cost, called rate-distortion optimization (RDO). However, the RDO operation requires the huge computational power. To fasten RDO processing, we proposed two algorithms: one is adaptive intra/inter coding, and the other is early SKIP prediction. Experimental results show that the former and the latter can significantly reduced encoding time about 24% and 17%, respectively, with only negligible coding performance degradation. Based on the adaptive algorithm, a real-time VLSI architecture of both H.264 encoder and decoder is developed with cell-based design. The architecture had been verified by FPGA prototyping in success. The gate count is about 76k and 42k for encoder and decoder respectively.

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