立體積體電路裝置

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

101100310

專利證號

I 467736

專利獲證名稱

立體積體電路裝置

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2015/01/01

技術說明

一種立體積體電路裝置，包含第一晶粒、第二晶粒、複數導電通道，及焊墊單元。第一晶粒包括主要電路，第二晶粒與第一晶粒堆疊並包括避免主要電路受破壞的保護電路，導電通道自保護電路延伸至與第一晶粒的主要電路連接，焊墊單元包括與導電通道連接而對主要電路及保護電路傳送來自外界電訊號的輸出入焊墊（I/O pad）。本發明以主要電路與保護電路分設相異基板，再堆疊及配合導電通道電連接兩晶粒，而不需如目前所有電路置於同一晶片時，須保留預定距離以防止保護電路產生的脈衝影響主要電路導致過熱或失效，並進而有效減少整體的面積。 A three-dimensional integrated circuit device includes the first chip, the second chip, a plurality of conductive channels, and a pad unit. The first chip includes a major circuit, and the second is stacked over the first chip, and includes a protecting circuit that avoids the major circuit being destroyed. The conductive channels extend from the protected circuit to the major circuit and couple with the major circuit. The pad unit includes a I/O pad which couples with the conductive channels and transmits a signal to the major channel and the protected circuit. The invention sets the major circuit and the protected circuit on the different substrates, and then stacks the chips which couple with the conductive channels. It doesn’t need to leave a specific distance to keep the major circuit from over-hot or breaking down, and reduce the whole area.

備註

連絡單位 (專責單位/部門名稱)

智慧財產權中心

連絡電話

03-5738251

網址