靜電防護結構

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

098105904

專利證號

I 449157

專利獲證名稱

靜電防護結構

專利所屬機關 (申請機關)

健行學校財團法人健行科技大學

獲證日期

2014/08/11

技術說明

0.18mm互補金氧半製程中金氧半電晶體的短路/置入型井區基底接觸點佈局會因為等效基底電阻短路而嚴重危害其靜電防護強度，因此本發明對此佈局限制議題發展新的基底接觸點設計型態。在多指狀N型電晶體中沿通道寬度方向的分散式基底接觸點設計可以改善其靜電防護能力，分散式基底接觸點設計經人體放電模式靜電量測證實靜電防護臨界點在短路接觸型1.8V NMOS方面提高2倍，在短路接觸型3.3V NMOS方面靜電放電耐壓提高18%，在置入型3.3V NMOS方面靜電能力提高5倍。 In 0.18μm CMOS process butting or inserted layout of substrate / well pickups of MOSFETs strictly degrades ESD robustness owing to the effective substrate resistance shorting effect. Therefore, this work studies this layout restriction issue and develops new pickup design style to improve this ESD degradation. Splitting butting / inserted well / substrate pickups along the channel width direction in multi-finger NMOS layout structures can improve the ESD performance. The measured data of the new splitting pickup improvement confirmed that the ESD threshold level increases by 2 times for butting-pickup 1.8V devices and increases by 18% for butting-pickup 3.3V devices; the ESD threshold level increases by 5 times for the inserted-pickup 3.3V devices.

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