以單一步驟製作一體成型金氧半閘堆疊結構及其元件之方法Method for manufacturing gate stack structure in insta-metal-oxide-semiconductor field-effect-transistor

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

14/619,594

專利證號

US 9,299,796 B2

專利獲證名稱

以單一步驟製作一體成型金氧半閘堆疊結構及其元件之方法Method for manufacturing gate stack structure in insta-metal-oxide-semiconductor field-effect-transistor

專利所屬機關 (申請機關)

國立中央大學

獲證日期

2016/03/29

技術說明

本技術提供了以一個步驟，一次到位來製作一體成型之鍺/二氧化矽/鍺金氧半結構的方法：經由選擇性氧化矽鍺合金奈米柱所製作之鍺奈米球，於過氧環境下，會鑽入下方的氮化矽層，最後碰觸到矽基板，自然形成由上而下分別為鍺奈米球/二氧化矽/鍺殼之異質堆疊結構。以此法所形成之熱穩定性安定、界面性質良好的鍺/二氧化矽界面，可做為核心閘極結構並實現高品質且一體成型之鍺金氧半電晶體。除了鍺具有較高的載子遷移率外，同時可避免以及解除了目前鍺金氧半電晶體不斷遭遇到的棘手界面問題，並可與現行矽製程技術相容，直接與矽元件整合，甚至是取代矽元件實現功能性電路。 A unique method for forming self-aligned Ge/SiO2/Ge metal-oxide-semiconductor (MOS) gate structure in using a single fabrication step is proposed. The Ge QD formed through thermal oxidization of Si1-xGex nanopillar would burrow into Si3N4 buffer layer as given sufficient oxidation time and eventually contact with specific regions of the underlying Si substrate, forming a self-aligned Ge-QD/SiO2/Ge-shell heterostructure. Such a Ge/SiO2 interface is thermally stable and satisfactorily reliable for being the heart of gate stack in realizing high-performance Ge MOS filed-effect-transistor (MOSFET). In addition to the benefit of high intrinsic carrier mobility in Ge, this approach is completely CMOS compatible and free from the troublesome interfacial issue, providing direct integration of Ge MOSFETs with prevailing Si devices in functional circuits.

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