轉導放大器、可編程重組之全差動電壓感測放大器以及可編程重組之全差動電容感測放大器Operational Transconductance Amplifier, Reconfigurable Fully Differential Voltage Sensing Amplifier And Reconfigurable Fully Differential Capacitive Sensing Amplifier | 專利查詢

轉導放大器、可編程重組之全差動電壓感測放大器以及可編程重組之全差動電容感測放大器Operational Transconductance Amplifier, Reconfigurable Fully Differential Voltage Sensing Amplifier And Reconfigurable Fully Differential Capacitive Sensing Amplifier


專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

103101645

專利證號

I 531159

專利獲證名稱

轉導放大器、可編程重組之全差動電壓感測放大器以及可編程重組之全差動電容感測放大器Operational Transconductance Amplifier, Reconfigurable Fully Differential Voltage Sensing Amplifier And Reconfigurable Fully Differential Capacitive Sensing Amplifier

專利所屬機關 (申請機關)

國立臺灣科技大學

獲證日期

2016/04/21

技術說明

此發明為一個可抑制直流準位偏壓飄移的低功耗低雜訊放大器,其增益及頻寬可重組編程、高動態範圍、高線性度、高能源效益、低雜訊、低功耗、低雜訊效率因素、利用懸浮閘電晶體技術於低雜訊放大器之設計。其中的雙差動對輸入能使電路消耗等量電流的條件下,轉導值增為兩倍,電路頻寬也增為兩倍。而將懸浮閘技術運用於共模回授電路中,使得回授電路不需消耗額外能量的情況可以利用全差動架構,可增加其共模雜訊抑制比和電源波紋抑制比。本發明經實際設計、製作、及量測後,量測所得之雜訊效率因素為1.96,比目前文獻所發表之電路效能為佳。 A reconfigurable fully differential biopotential amplifier utilizing floating-gate transistors is proposed in this patent. Because of the employment of complementary differential pairs with current reuse technique, the theoretical limit for the noise efficiency factor of this amplifier is below 1.5, which has met the physical limit. Floating-gate transistors are employed to program the amplifier low-frequency cutoff corner and to implement the common-mode feedback without consuming any extra power. The chip was tested under different configurations with the bandwidth of 100Hz, 1KHz, and 10KHz. The measured noise efficiency factors in these settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date.

備註

連絡單位 (專責單位/部門名稱)

技術移轉中心

連絡電話

02-2733-3141#7346


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