MEMORY UNIT WITH ADAPTIVE CLAMPING VOLTAGE SCHEME AND CALIBRATION SCHEME FOR MULTI-LEVEL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

16/987,372

專利證號

US 11,195,090

專利獲證名稱

MEMORY UNIT WITH ADAPTIVE CLAMPING VOLTAGE SCHEME AND CALIBRATION SCHEME FOR MULTI-LEVEL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2021/12/07

技術說明

A memory unit is controlled by a word line, a reference voltage and a bit-line clamping voltage. A non-volatile memory cell is controlled by the word line and stores a weight. A clamping module is electrically connected to the non-volatile memory cell via a bit line and controlled by the reference voltage and the bit-line clamping voltage. A clamping transistor of the clamping module is controlled by the bit-line clamping voltage to adjust a bit-line current. A cell detector of the clamping module is configured to detect the bit-line current to generate a comparison output according to the reference voltage. A clamping control circuit of the clamping module switches the clamping transistor according to the comparison output and the bit-line clamping voltage. When the clamping transistor is turned on by the clamping control circuit, the bit-line current is corresponding to the bit-line clamping voltage multiplied by the weight.

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