降低電流路徑熱應力之晶片

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

105127157

專利證號

I 613775

專利獲證名稱

降低電流路徑熱應力之晶片

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2018/02/01

技術說明

本技術提供一種降低電流路徑熱應力之晶片，散熱技術如TWI316750專利為在覆晶晶片與封裝基板間製備多個散熱區域增加散熱路徑藉以降低焊料接合時所造成之熱應力。針對原件工作時電流產生之熱應力，本技術則在電流路徑周遭設置奈米結構可使較小的面積得以承受一預定電流值工作所產生之熱應力，分別具有1、2及3微米深度之奈米垂直線狀結構群之晶片，相對於不具有奈米垂直線狀結構群之一習知晶片(對照組)實施熱應力比較後，很明顯地，本發明的晶片在距一電流路徑側邊1-2微米處所量測到的熱應力數值遠低於在該習知晶片的對應量測處(距一電流路徑側邊1-2微米處)所量測到的熱應力數值。依量測結果得知，利用本技術使縮小之晶片依然能夠承受相同之工作電流所產生之熱應力。 The present invention relates to a chip reducing thermal stress of a current path thereon. Thermal disperse patent as TWI316750 shows inserting many thermal dispersion region between flip-chip and substrate as a way of expanding thermal dispersion path to reduce the thermal stress caused by metal contacts when soldering. But, thermal stress will not just caused when soldering but also by the current when chips working. To reduce the thermal stress caused by operating chip, a novel chip with nanowires around current path was introduced in order to make smaller chip can bear certain amount of current. A regular chip and three chips with nanowires in 1μm, 2μm and 3μm depth were set under operation. Obviously, the proposed new invention chips with nanowires have much lower thermal stress than the regular one at the region 1-2μm away from the current path. As a result, using this new invention can make smaller chips bear the same operation current thermal stress as regular size chips.

備註

本會(收文號1120045669)同意該校112年7月13日清智財字第1129005239號函申請終止維護專利(國立清華大學)

連絡單位 (專責單位/部門名稱)

智財技轉組

連絡電話

03-5715131-62219

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