發明
中華民國
103115815
I 511400
可提升閂鎖防疫能力之主動式防護電路及主動防護環電路
國立交通大學
2015/12/01
一種主動式防護電路,適於一積體電路進行閂鎖測試時提升其閂鎖防疫能力。此主動式防護電路包含有一輸入輸出電路與一主動防護環電路,輸入輸出電路係透過一輸入節點接收一注入電流,並在該注入電流之激發下產生一基底電流;主動防護環電路連接於輸入輸出電路與一內部電路之間,並偵測該注入電流係為一正電流脈衝或負電流脈衝。當注入電流之電流強度高於一門檻值時,主動防護環電路係控制輸入輸出電路產生一補償基底電流之電流大小,以達成避免該內部電路閂鎖發作之效用。 An active guard ring structure is provided, which is applicable to improving latch-up immunity during the latch-up current test (I-test). The proposed active guard ring structure comprises an I/O circuit and an active protection circuit, wherein the I/O circuit receives a trigger current via an input pad and generates a corresponding bulk current since being triggered. The active protection circuit, connected between the I/O circuit and a core circuit, detects whether the trigger current is a positive or negative current pulse. When an intensity of the trigger current is larger than a threshold value, the active protection circuit controls the I/O circuit to provide a compensation current so as to compensate the bulk current and to reduce the current flowing into or sourced from the core circuit, thereby preventing the core circuit from encountering latch-up.
本會(收文號1110027136)回應該校111年5月12日陽明交大研產學字第1110015716號函申請終止維護專利(國立陽明交通大學)
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