INPUT-PATTERN AWARE REFERENCE GENERATION SYSTEM AND COMPUTING-IN-MEMORY SYSTEM INCLUDING THE SAME

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

16/029,350

專利證號

US 10,340,003 B1

專利獲證名稱

INPUT-PATTERN AWARE REFERENCE GENERATION SYSTEM AND COMPUTING-IN-MEMORY SYSTEM INCLUDING THE SAME

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2019/07/02

技術說明

運用於非揮發性運算系統之使用電阻式記憶體之非揮發性邏輯電路開發與探索 In view of the aforementioned problems of the prior art, one objective of the present invention provides an input-pattern aware reference generation system for a memory cell array having a plurality of word lines crossing a plurality of bit lines, the plurality of word lines being selectively activated by an input signal such that each of the plurality of bit lines generates a computational result of multiply-and-accumulate (MAC) computation, the system including: an input counting circuit, receiving the input signal of the memory cell array, discovering input activated word lines according to the input signal and generating a number signal representing a number of the input activated word lines; a reference array, including a plurality of reference memory cells storing a predetermined set of weights; and a reference word line control circuit, electrically connected between the input counting circuit and the reference array, the reference word line control circuit controlling the reference array to generate a plurality of reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array according to the number signal. Preferably, the reference array may include a plurality of reference bit lines, and the predetermined set of weights is arranged such that the plurality of reference bit lines each represents a possible MAC computational result of a combination of 0’s and 1’s stored in each memory cell of the memory cell array. Preferably, the plurality of reference signals may be generated according to outputs of the reference bit lines. Preferably, the plurality of reference signals each may represent an average of two neighboring outputs of the reference bit lines.

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