DYNAMIC BIT-LINE CLAMPING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND CLAMPING METHOD THEREOF

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

16/115,582

專利證號

US 10,510,386 B1

專利獲證名稱

DYNAMIC BIT-LINE CLAMPING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND CLAMPING METHOD THEREOF

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2019/12/17

技術說明

運用於非揮發性運算系統之使用電阻式記憶體之非揮發性邏輯電路開發與探索 According to one aspect of the present disclosure, a dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal. The dynamic bit-line clamping circuit for the computing-in-memory applications includes a clamping node, a first clamping unit, a second clamping unit, a first feedback controlling unit and a second feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage. The second clamping unit includes a first top transistor, a second top transistor and a switch. The first top transistor is electrically connected between the clamping node and the power source voltage. The second top transistor is electrically connected between the clamping node and the power source voltage. The switch is electrically connected between the clamping node and the second top transistor. The first feedback controlling unit is electrically connected to the first clamping unit and the bit line. The first feedback controlling unit generates a controlling signal to control the first clamping unit according to a voltage level of the bit line. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node according to the at least one reference signal.

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