低電壓差動訊號模式發射與接收電路

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

105126291

專利證號

I 599173

專利獲證名稱

低電壓差動訊號模式發射與接收電路

專利所屬機關 (申請機關)

元智大學

獲證日期

2017/09/11

技術說明

為了讓低電壓差動訊號式介面電路能在更低的供應電壓下操作，並達到更高傳輸率，加入一信號準位調整電路來對改變資料準位。位移後的資料訊號可直接忽略驅動電晶體的臨界電壓，使其信號擺幅能完全作為驅動電晶體的閘級過載驅動電壓。更高的電路頻寬與更低的供應電壓都可藉此達成。一般而言，為確保不同操作條件下都輸出規定準位，介面電路會加入以控制開關與縮小的介面電路複製單元組成擺幅調整電路，但操作頻寬會因控制開關的寄生參數而大幅降低。為兼顧擺幅調整與操作頻寬，將驅動電路的擺幅控制信號的準位也透過準位調整電路進行位移。以台積電0.18mm CMOS製程進行實體電路設計並實現一測試晶片。在0.35V的單電源供應下，整個介面電路系統的總電流消耗為1mA，資料傳輸頻率達到0.6Gbps。 To realize a low-voltage-differential-signaling (LVDS) I/O for ultra-low supply voltage and ultra-high speed applications, a novel level shifter is added to shift the levels of data. The level of shift and the threshold voltage of the driving transistors could be countervailed each other, so the signal swing are fully used as the gate over-drive voltage of the driving transistor. As a result, both a higher bandwidth and a lower supply voltage could be achieved. The control switches and divided replica I/O cells would be added to original I/O. With the parasitic parameters of control switches, the bandwidth of I/O would be highly reduced. The level shifter is also used to boost the level of the control signals to highly release the performance trade-off between bandwidth and tuning range of output swing. In 0.18um CMOS process, one test-chip is realized to verify the proposed patents. Under single 0.35V power supply, the total current consumption is 1mA and achieve a bit rate of 0.6Gbps

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