INPUT-SHAPING METHOD AND INPUT-SHAPING UNIT FOR GROUP-MODULATED INPUT SCHEME IN COMPUTING-IN-MEMORY APPLICATIONS

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

17/200,927

專利證號

US 11,621,723

專利獲證名稱

INPUT-SHAPING METHOD AND INPUT-SHAPING UNIT FOR GROUP-MODULATED INPUT SCHEME IN COMPUTING-IN-MEMORY APPLICATIONS

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2023/04/04

技術說明

運用於非揮發性運算系統之使用電阻式記憶體之非揮發性邏輯電路開發與探索 According to one aspect of the present disclosure, a voltage-enhanced-feedback sense amplifier of a resistive memory is configured to sense a first bit line and a second bit line. The voltage-enhanced-feedback sense amplifier of the resistive memory includes a voltage sense amplifier and a voltage-enhanced-feedback pre-amplifier. The voltage sense amplifier has a first input node and a second input node. The voltage-enhanced-feedback pre-amplifier is electrically connected to the voltage sense amplifier. The voltage-enhanced-feedback pre-amplifier includes a first bit-line amplifying module and a second bit-line amplifying module. The first bit-line amplifying module has a first internal node. The second bit-line amplifying module has a second internal node. The first bit-line amplifying module includes a first transistor, a first capacitor, a second transistor, a third transistor, a fourth transistor and a first switching element. The first transistor is coupled to a read voltage, the first bit line and the second input node. The first capacitor is coupled between the first bit line and the first internal node. The second transistor is coupled between a power supply voltage and the first internal node. The third transistor is coupled to the first input node, the first internal node and a ground voltage. The fourth transistor is coupled to the power supply voltage, the first input node and the first internal node. The first switching element is coupled between the first input node and the first internal node. The second bit-line amplifying module includes a fifth transistor, a second capacitor, a sixth transistor, a seventh transistor, an eighth transistor and a second switching element. The fifth transistor is coupled to the read voltage, the second bit line and the first input node. The second capacitor is coupled between the second bit line and the second internal node. The sixth transistor is coupled between the power supply voltage and the second internal node. The seventh transistor is coupled to the second input node, the second internal node and the ground voltage. The eighth transistor is coupled to the power supply voltage, the second input node and the second internal node. The second switching element is coupled between the second input node and the second internal node. There is a read voltage difference between a voltage level of the first bit line and a voltage level of the second bit line. There is a margin enhanced voltage difference between a voltage level of the first input node and a voltage level of the second input node, and the margin enhanced voltage difference is greater than the read voltage difference.

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