REFERENCE-FREE MULTI-LEVEL SENSING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS, REFERENCE-FREE MEMORY UNIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND SENSING METHOD THEREOF

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

16/109,734

專利證號

US 10,410,690 B1

專利獲證名稱

REFERENCE-FREE MULTI-LEVEL SENSING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS, REFERENCE-FREE MEMORY UNIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND SENSING METHOD THEREOF

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2019/09/10

技術說明

運用於非揮發性運算系統之使用電阻式記憶體之非揮發性邏輯電路開發與探索 According to one aspect of the present disclosure, a reference-free multi-level sensing circuit for computing-in-memory applications is controlled by a first bit line and a second bit line. The reference-free multi-level sensing circuit for the computing-in-memory applications includes a voltage sense amplifier, a precharging unit and an encoding unit. The voltage sense amplifier is electrically connected to the first bit line and the second bit line. The precharging unit is electrically connected to the voltage sense amplifier. The encoding unit is electrically connected to the voltage sense amplifier. The encoding unit includes a first register, a second register, a third register, a fourth register and an encoder. The first register is electrically connected to the voltage sense amplifier and outputs a first register output value. The first register output value feedback controls the precharging unit so as to enable the precharging unit to precharge one of the first bit line and the second bit line according to the first register output value. A voltage level of the one of the first bit line and the second bit line is lower than a voltage level of the other one of the first bit line and the second bit line. The second register is electrically connected to the voltage sense amplifier and outputs a second register output value. The third register is electrically connected to the second register and outputs a third register output value. The fourth register is electrically connected to the third register and outputs a fourth register output value. The encoder is electrically connected to the second register, the third register and the fourth register. The encoder generates a plurality of encoded values according to the second register output value, the third register output value and the fourth register output value, and the encoded values and the first register output value are formed a multi-bit signal to estimate voltage levels of the first bit line and the second bit line.

備註

連絡單位 (專責單位/部門名稱)

智財技轉組

連絡電話

03-5715131-62219

網址