鎖相迴路PHASE-LOCKED LOOP

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

13/900,556

專利證號

US 8,810,291 B2

專利獲證名稱

鎖相迴路PHASE-LOCKED LOOP

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2014/08/19

技術說明

本發明提出接收機式鎖相迴路架構，傳統上高頻鎖相迴路多採用注入鎖定式除頻器(Injection locked divider) 作為預先除頻器 (Prescaler)，在回授信號路徑上提供降頻之功能。多級串接時易造成注入鎖定除頻器之中心頻率偏移失焦 (misalignment)及無法正確除頻之問題，造成迴路無法正確鎖定 。本發明中高頻之頻率預先除頻器 (prescaler) 將利用混波器進行取代，且利用接收信號強度偵測器對降頻後之信號進行強度偵測，藉此進行頻率掃描及快速鎖定之功能。利用本技術已成功開發完成 160 GHz 之鎖相迴路，並完成晶片量測，本技術可應用在毫米波及THz 信號產生器之實現上。 A receiver-based phase-locked loop (PLL) architecture is presented. Conventionally, high frequency phase-locked loops utilize injection locked frequency divider as a prescaler, so as to provide low frequency feedback signal for phase and frequency comparison. However, frequency misalignment in multi-stage cascaded injection locked frequency divider can lead to imporper operation of the divider and cause the loop may fail to lock. In this invention, high frequency prescaler in the PLL is replaced by a mixer for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI), which detects the signal strength after down conversion, for automatically frequency sweeping and fast locking. A 160 GHz PLL based on the proposed architecture has been successfully implemented and verified. The proposed technique can be utilized for millimeter wave and THz signal generator.

備註

本部(收文號1100065219)同意該校110年10月27日陽明交大研產學字第1100036963號函申請終止維護專利(陽明交大)

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