估測逐次漸近類比數位轉換器中數位類比轉換器內電容權重誤差之方法與其應用於校正該逐次漸進類比數位轉換器METHOD FOR ESTIMATING CAPACITANCE WEIGHT ERRORS AND SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER USING THE SAME

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

14/033,773

專利證號

US 8,907,826 B2

專利獲證名稱

估測逐次漸近類比數位轉換器中數位類比轉換器內電容權重誤差之方法與其應用於校正該逐次漸進類比數位轉換器METHOD FOR ESTIMATING CAPACITANCE WEIGHT ERRORS AND SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER USING THE SAME

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2014/12/09

技術說明

本發明提出一種估測逐次漸近類比數位轉換器中數位類比轉換器內電容權重誤差之方法，用以估計數位類比轉換器的電容的電容權重誤差。該待校逐次漸近類比數位轉換器包括比較器、電容組、開關組與控制器，其中電容組包括一個具有多個電容的主電容陣列與一個包含多個已知權重電容的子電容陣列，前述主電容陣列包含一輔助電容以及一個電容之間的比例可以成2的冪次方關係的電容陣列，且該輔助電容小於主電容陣列之其他電容，前述子電容陣列電容的已知權重可以成2的冪次方關係。控制器用以控制開關組，依序重複執行主電容陣列的預先充電、將電荷重新分布於主電容陣列與子電容陣列、與主電容陣列及子電容陣列的逐次逼近二元搜尋法，並依所得結果計算主電容組內各個電容的電容權重誤差值。所得之該等電容權重誤差值可用以校正該逐次漸近類比數位轉換器的輸出。 A method to estimate the ratio errors of the capacitors in the digital-to-analog converter of a SAR ADC is provided. The SAR ADC comprises a comparator, a capacitor set, a switch set and a controller, wherein the capacitor set has a main capacitor array and a sub capacitor array. The main capacitor array comprises capacitors and an assistant capacitor whose capacitance value is less than that of the other capacitors in the main capacitor array. The sub capacitor array contains capacitors whose weights are known with sufficient accuracy. The controller is used to control the switch set and repetitively performs the error estimation procedures until all capacitor ratio errors are calculated. Each error estimation procedure provides a digital error output. The controller calculates the ratio errors of the capacitors in the main capacitor array according to the digital error outputs. The obtained capacitor ratio errors can be used to calibrate the primary output of the SAR ADC.

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