發明
中華民國
102116900
I 501551
相位切換除頻器電路FREQUENCY DIVIDER CIRCUIT
國立中興大學
2015/09/21
一種高解析低雜訊多相位除頻器,其主架構為注入鎖定除頻器,其由N個雙端反向器組成的環振盪器(ring oscillator)。設計環振盪器振盪頻率使其接近在除頻的中心頻率,並且注入時脈信號與環振盪器輸出訊號的諧波(harmonics)混合,藉以產生與環振盪器振盪頻率相近頻率的信號,此信號會拉扯環振盪器的輸出並鎖定之。我們將注入鎖定除頻器結合相位選擇使其解析度變成四倍,所採用的相位選擇電路則是由數位的累加器搭配解碼器和開關所構成。 The injection-locked architecture of a high resolution, low noise and muti-phase divider is injection-locked divider employs the ring oscillator which is composed of N stage differential inverter. We make the free running frequency of ring oscillator being at the center of dividing frequency. Furthermore, the divider mixes the injected clock signal with output harmonics, and then generates a tone approach to ring oscillator free running frequency. The output tone will pull the ring oscillator’s tone and lock it. In this work, we combine the injection-lock divider with a phase selection to produce quadruple resolution. The phase selection circuit is composed of a digital accumulator, a demultiplexer and switches.
本部(收文號1090023163)同意該校109年4月20日興產字第1094300209號函申請終止維護專利(中興)
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