整合矽控整流器雙極電晶體電路

專利類型

新型

專利國別 (專利申請國家)

中華民國

專利申請案號

101122260

專利證號

I 474465

專利獲證名稱

整合矽控整流器雙極電晶體電路

專利所屬機關 (申請機關)

健行學校財團法人健行科技大學

獲證日期

2015/02/21

技術說明

本發明主要提供一種能夠在互補金氧半製程中，具備高於操作電壓之保持電壓的整合矽控整流器雙極電晶體電路。所述整合矽控整流器雙極電晶體電路係由含有浮接P+擴散區域或浮接N+擴散區域的雙極電晶體結構，與作為開關的金氧半電晶體閘極覆蓋前述浮接區域所構成，另外閘極進一步與電阻電容電路耦合；雙極電晶體其基本設計參數為陽極∕陰極和浮接P+∕N+擴散區域間距L，以及浮接P+∕N+擴散區域的寬度W。依據靜電打擊或正常操作情況以決定導通金氧半開關與否調整增加減短浮接擴散區域寬度W。藉由調整在此電路中金氧半電晶體的通道長度和它的汲源極範圍尺寸，得到足夠的靜電強健度和免除栓鎖的保持電壓。 A new Silicon-Controlled Rectifier (SCR)-incorporated BJT circuit with a higher holding voltage than the operating voltage is developed for ESD protection in a 0.18μm process. This circuit consists of a floating P+ anode or N+ cathode in the BJT structure with a MOS gate capped above the floating region as a switch, and this gate is further coupled with an RC circuit The main device design parameters concerning ESD in this circuit are the spacing L between the anode/cathode and floating P+ anode/N+ cathode, as well as the width W of the floating P+ anode/N+ cathode. The RC gate-coupled circuit could determine MOS switch turn on or not to adjust width W size of the floating region according to ESD stress or normal IC operating situation. We can obtain sufficient ESD protection robustness and latchup-free DC holding voltage by adjustment of the MOS channel length and its drain region size in this circuit.

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(03)4581196-3110

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