積體化摻雜通道擬晶性異質結構場效電晶體

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

096115507

專利證號

I 336130

專利獲證名稱

積體化摻雜通道擬晶性異質結構場效電晶體

專利所屬機關 (申請機關)

國立高雄師範大學

獲證日期

2011/01/11

技術說明

本發明揭示一種磷化銦鎵/砷化銦鎵(InGaP/InGaAs)增強/空乏式積體化摻雜通道擬晶性異質結構場效電晶體。藉由選擇性之蝕刻製程步驟，可於同一基板上同時製作增強式與空乏式場效電晶體。此空乏式場效電晶體具有雙摻雜通道結構，而增強式場效電晶體僅有單一摻雜通道結構。由於InGaAs應變通道為已摻雜結構層，且InGaP/InGaAs異質接面具有大的導電帶不連續值，將於InGaAs 應變通道內形成二維電子雲氣(2DEG)，這將實質地增加通道的有效濃度且使通道濃度隨閘極偏壓而調變。本發明元件同時具有摻雜通道電晶體及高電子遷移率電晶體之特點，且汲-源極(drain-to-source)飽和電壓很低，於反向器電路製作時可有效地提升其雜訊邊界。 The integration of InGaP/InGaAs enhancement/depletion pseudomorphic doped-channel field-effect transistors (DCFETs) is disclosed by the present invention. By way of the selectively etching process, the enhancement/depletion pseudomorphic integrated devices could be fabricated on the identical chip. The double-doped channels are formed in the depletion-mode device, while only one channel appears in the enhancement-mode device. Because the presence of the considerable conduction band discontinuity at InGaP/InGaAs heterojunction, it forms two dimensional electron gas (2DEG) in the InGaAs strain channel, which increases the concentration in InGaAs active channel and the carriers could be modulated with the applied gate bias. Thus, the devices perform with the combination of DCFETs and high electron mobility transistors. In addition, due to the low drain-to-source saturation voltage, the noise margin is substantially increased for the inverter circuit applications.

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