發明
中華民國
103121581
I 492083
具應力放大作用之閘極配置元件
中原大學
2015/07/11
目前元件在不同的電路圖案設計與考量微影製程之穩定度,製造上皆會引入諸如源汲集方向上等間距增加複數個複晶矽結構,以及縮減不同程度之元件擴散區長度,當複雜製程程序與不同應變工程應力源導入元件時,致使提升元件電子遷移率能力之效能大幅降低,且由應變矽引致應力影響之元件性能參數將較難量測,尤其是當應力大小差距2至3個級距之不同應力源施予時,較弱應力源對元件性能影響之效應容易被較強者所掩蓋住。因此,導致應力源所施加之應力是否可增強或是減弱元件性能,不能容易地判斷和鑑別。有鑑於此,本發明提出新的啞複晶矽配置結構,用以放大與調控所需元件方向上的應力。根據此提出之新配置結構,上述既有技藝之缺點可被克服或予以緩解。 Current devices with different test patterns used to extract the effects, such as poly spacing effect(PSE) and length of diffusion (LOD) effect resulted from intrinsic stress impact, becomes more difficult when the complicated process and various stressors are introduced. Measured electrical data of devices designed for extracting the stress effects on the channel mobility gain are significantly indistinct-able especially when the stress of each individual stressor is differed by 2~3 orders in magnitude as the weaker ones are often masked the stronger ones. Hence, the impact levels of stress on boosting or harming the performance of MOS devices resulted from different stressor cannot be easily judged and differentiated. This invention discloses the novel dummy poly configurations amplify the stress magnitude along the direction of interest. By means of the proposed new configurations, the drawbacks are overcome or alleviated.
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