平移式電晶體邏輯電路Logic Circuit

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

12578538

專利證號

US 7,795,923 B1

專利獲證名稱

平移式電晶體邏輯電路Logic Circuit

專利所屬機關 (申請機關)

國立彰化師範大學

獲證日期

2010/09/14

技術說明

在本發明，我們提出新的基底傳輸閘型 (TG-based) AND 閘、TG-based OR 閘及其他平移式電晶體 (pass-transistor) 邏輯閘，與其他作者所發表的平移式電晶體邏輯閘比較，我們的閘為一新架構而且有較少的電晶體數目。所有該發明所提出的邏輯閘均運作在全振幅，而且與傳統CMOS邏輯閘比較，本發明的閘有較低的漏電流、較低的動態功耗及較短的延遲。將本發明的65nm閘與一般CMOS 65nm閘比較，我們發現本發明的閘平均能夠改善漏電流29.5%、動態功耗15.3%、傳輸延遲30.3%。 我們可用邏輯合成器來降低合成電路的功耗。實驗結果顯示，當標準元件庫內含我們所發明的邏輯閘時，Power Compiler工具最多能再進一步降低漏電流39.85%，降低動態功率 18.69%。 In this invent, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All the invented gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the conventional 65nm CMOS gates, the invented 65nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. Logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.

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04-7232105轉1858

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