具有奈米線通道之半導體元件的製程及藉此形成之半導體元件A MANUFACTURING METHOD OF A SEMICONDUCTOR COMPONENT WITH A NANOWIRE CHANNEL

專利類型

發明

專利國別 (專利申請國家)

日本

專利申請案號

特願 2012-082485

專利證號

特許 5532071

專利獲證名稱

具有奈米線通道之半導體元件的製程及藉此形成之半導體元件A MANUFACTURING METHOD OF A SEMICONDUCTOR COMPONENT WITH A NANOWIRE CHANNEL

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2014/05/09

技術說明

本發明以新穎的元件結構與製程技術開發出具全環繞閘極與提升源極/汲極結構之次10-nm奈米線通道場效電晶體，利用三明治結構所選用的兩種材料互相之間具有高度蝕刻選擇性比，且當三明治結構被蝕刻去除時，必須對所選用之奈米線材料與基材材料也同樣具高度選擇比來達成；藉由改變通道摻雜濃度高低與奈米線直徑大小，此元件能成為傳統接面式具全環繞閘極與提升源極/汲極結構之奈米線通道場效電晶體也可以成為新穎無接面式(Junctionless)具全環繞閘極與提升源極/汲極結構之奈米線通道場效電晶體，本發明主要目的是開發新穎的製程技術來製做具次10nm奈米線通道之高性能場效電晶體。 We propose a sub-10-nm nanowire (NW) channel field-effect transistor with gate-all- around and raised source / drain structure using novel device structure and fabrication method. The two materials in the dummy sandwich structure are mutually exclusive with regard to the wet-etching selectivity, where the NW and the substrate are also highly selective to the etching solution while removing the dummy sandwich structure. The proposed devices are not only traditional junction field-effect transistors but also novel junctionless field-effect transistors by changing the channel doping concentration and the diameter of NW. This patent is proposed for fabricating the high-performance field-effect transistor with sub-10-nm NW channel by using novel processing technologies.

備註

本部(收文號1090020336)同意該校109年4月6日交大研產學字第1091002952號函申請終止維護專利(交大)

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