場效電晶體結構

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

105113196

專利證號

I 574402

專利獲證名稱

場效電晶體結構

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2017/03/11

技術說明

本發明是有關於一種半導體元件，且特別是有關於一種場效電晶體結構。近年來，由於電晶體尺寸的微小化而產生許多新穎的製程技術，其中，無接面(junctionless，JL)場效電晶體(field effect transistor，FET)由於能有效減少短通道效應(short channel effect，SCE)以及寄生串聯電阻(parasitic series resistance)的影響，而被視為未來的主要發展方向之一。然而，無接面場效電晶體的製程困難度高，且具有可能使源極與汲極的串聯電阻過高而造成汲極電流下降等問題，因此，如何在簡化製程的同時還能達到更佳的電性表現是當前所面臨的課題。本發明提供一種場效電晶體結構，能減少臨界電壓滾降，且具有小的汲極引致能障降低(drain-induced barrier lowering，DIBL)、接近理想值的次臨界擺幅(subthreshold slope，SS)、高的開關電流比(on/off current ratio)、好的臨界電壓調變(threshold voltage modulation)能力、較低的低頻雜訊(low-frequency noise，LFN)、好的可靠度、低的漏電流、較小的串聯電阻以及較少的電流擁擠效應(Current Crowding Effect)。 The junctionless (JL) FET that can effectively lessen the impact of short channel effect and parasitic series resistance has been considered as one of the mainstream products.Nevertheless, it is difficult to manufacture the JL FET, and the overly high source/drain series resistance may lead to the decrease in the drain current. Therefore, how to achieve satisfactory electrical performance and simultaneously simplify the manufacturing process has become one of the challenges that the manufacturers face. The disclosure provides an FET structure that can prevent the issue of the roll-off of a threshold voltage and is characterized by a negligible drain-induced barrier lowering, the sub-threshold slope approximating to an ideal value, a high on/off current ratio, high threshold voltage modulation, reduced low-frequency noise, good reliability, low current leakage, small series resistance, and reduced current crowding effects.

備註

本會(收文號1120019924)同意該校112年4月7日陽明交大研產學字第1120010771號函申請終止維護專利(國立陽明交通大學)

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