增進穿隧式電晶體效能的磊晶穿隧層結構Enhanced Tunnel Field Effect Transistor

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

14/031,301

專利證號

US 8,853,824 B1

專利獲證名稱

增進穿隧式電晶體效能的磊晶穿隧層結構Enhanced Tunnel Field Effect Transistor

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2014/10/07

技術說明

本發明提出一種新的結構用以製作穿隧式電晶體，用以提升穿隧式電晶體特性，藉以達到降低元件功率損耗的目標。本發明利用與現有CMOS製程高度相容的磊晶穿隧結構，結合異質材料特性，搭配垂直方向的穿隧效應，有效提升穿隧式電晶體的效能，同時保有此元件低漏電與低次臨界擺幅的特性。本發明利用上述特點製作出較高效能的穿隧式電晶體，可有效提升穿隧式電晶體元件特性。本發明考慮實際製作層面，結合上述各點可望實際製作出高效能之穿隧式電晶體。 The epitaxial tunneling layer (ETL) structure of this invention applies the CMOS fabrication process and improves the tunneling current of the device by lowering the tunneling barrier with low band gap material as the ETL. The tunneling orientation of this structure is the same as the electric field direction modulated by gate which makes the better device characteristics, and the overlap region of the ETL and source/drain could enhance the tunneling area which makes the higher tunneling current. The fabrication of this device structure could be highly compatible with the CMOS gate-last process. The advantages of the ETL structure are low power consumption, high performance and easier to fabricate.

備註

本部(收文號1100065219)同意該校110年10月27日陽明交大研產學字第1100036963號函申請終止維護專利(陽明交大)

連絡單位 (專責單位/部門名稱)

智慧財產權中心

連絡電話

03-5738251

網址