利用缺陷所形成的記憶體MEMORY FORMED BY USING DEFECTS

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

12/617,516

專利證號

US 8,009,479 B2

專利獲證名稱

利用缺陷所形成的記憶體MEMORY FORMED BY USING DEFECTS

專利所屬機關 (申請機關)

國立臺灣大學

獲證日期

2011/08/30

技術說明

本發明係藉由偵測電晶體的累積區電流的大小來判斷其邏輯狀態。一般的薄膜式電晶體(TFT)的製程中，在沉積非晶矽薄膜後，利用雷射熱退火使該非晶矽薄膜形成一複晶矽薄膜，而缺陷則形成於該複晶矽薄膜晶粒的邊界。以p型主動區與n+摻雜的汲極與源極為例，當施加一負電壓於閘極且施加一正電壓於汲極時，該p型主動區內與該汲極交接處使電子從價電帶穿隧至導電帶，而電洞被主動區內的缺陷捕獲，在通道中形成能障，因而使該累積區電流變小，藉此可表示不同的邏輯狀態。本發明之記憶體係在電晶體關閉的狀態讀取該累積區電流，因此比習知記憶體(在導通時讀取)大幅降低功耗。本發明之記憶體為非揮發性記憶體，故不需刷新而能降低功率消耗。 This invention is for deciding logic state of transistors by detecting current in accumulation region. To give an example, as for p-type active region and n+doped source and drain, while applying a negative voltage on the gate and applying a positive voltage on the drain, the valence band electrons tunnels into conduction band near the junction between p-type active region and the n+drain Then, the holes are trapped in the defects, and the energy barrier height for hole transport increases. Therefore, the drain current in the accumulation region decreases, that can represent different logic state. The memory device in this invention is read-out in the accumulation region when the transistor is turned-off. Therefore, the power consumption during read is reduced as compared to traditional memory devices. In addition, the proposed memory devices are non-volatile and do not need to refresh the data. As a result, the power consumption can be further reduced.

備註

本部(第1080018808號)同意該校108年03月20日校研發字第1080019626號函申請終止維護案。

連絡單位 (專責單位/部門名稱)

產學合作總中心

連絡電話

33669945

網址