發明
美國
14/930,768
US 10,213,986 B2
Electric connection and method of manufacturing the same
國立成功大學
2019/02/26
本發明為應用於3D IC之矽穿孔連通製程中的一種Cu對Cu連結技術,可生成一具有高延性的Cu對Cu接點,且製程簡易。三維度積體電路構裝(3D IC)是目前全球半導體大廠競相發展的技術,也是國內積體電路製造與封測產業維持競爭力的關鍵。國內的各半導體大廠如台積電、日月光、矽品、力成等近幾年皆積極架構2.5D與3D IC封測產能,除此之外包括三星、爾必達、英特爾等公司都已同樣投入3D IC的研發和生產。台灣因半導體產業鏈完整,其生態優勢讓台灣在3D IC的發展上贏得商機的機會很大。在3D IC構裝中,矽晶片透過垂直堆疊的方式連結,可大幅縮小元件體積、增加效率、降低能量消耗與提高功能性。其中,矽穿孔連通為3D IC之核心科技,其關鍵製程又可包含晶圓薄化、直通矽穿孔、與銅對銅連結。而銅對銅連結可分為直接擴散接合法與微凸塊接合法兩大類,前者不但需要複雜的銅基材前處理,於接合時所須的高壓不但耗費成本又可能對電子元件造成損害。而微凸塊接合法則為相對經濟且成熟的製程。本專利技術是以微凸塊接合法為基礎,引入新的材料與製程,可在低溫下形成一高延性銅對銅固態接點,且不需複雜的表面處理或平坦化等製程。 This invention can be applied to the Cu-to-Cu bonding process in 3D IC TSV interconnection. 3D IC is the most important technology for the electronic packaging industry. Domestic manufacturers as well as global competitors have put much efforts in building the 3D IC testing framework in the past few years. Cu-to-Cu bonding for TSV interconnection is an essential process for vertical integration in 3D IC. Direct diffusion bonding and micro-bumping are two major approaches, but the former requires high pressure and strict surface pretreatment, so the latter is more feasible. Micro-bumping with Sn-based solders is a conventional method; however, brittle intermetallic compound formation causes significant reliability concerns. Our method is similar to micro-bumping, but we successfully fabricate a fully ductile Cu-to-Cu joints under moderate processing temperatures and pressures. Only conventional UBM electroplating and simple polishing process were required for the Cu substrates.
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