MEMORY STRUCTURE WITH INPUT-AWARE MAXIMUM MULTIPLY-AND-ACCUMULATE VALUE ZONE PREDICTION FOR COMPUTING-IN-MEMORY APPLICATIONS AND OPERATING METHOD THEREOF

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

17/361,343

專利證號

US 11,416,146

專利獲證名稱

MEMORY STRUCTURE WITH INPUT-AWARE MAXIMUM MULTIPLY-AND-ACCUMULATE VALUE ZONE PREDICTION FOR COMPUTING-IN-MEMORY APPLICATIONS AND OPERATING METHOD THEREOF

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2022/08/16

技術說明

A memory structure with input-aware maximum multiply-and-accumulate value zone prediction for computing-in-memory applications includes a memory array, an input-aware zone prediction circuit and an analog-to-digital converter. An input-aware maximum partial multiply-and-accumulate value voltage generator is configured to generate a maximum partial multiply-and-accumulate value according to at least one input value. A prediction-aware global reference voltage generator is configured to generate a plurality of global reference voltages, a maximum reference voltage and a selected minimum reference voltage. A maximum partial multiply-and-accumulate value zone detector is configured to generate a zone switch signal by comparing the maximum partial multiply-and-accumulate value and the global reference voltages. The analog-to-digital converter is configured to convert an analog multiply-and-accumulate output value of the memory array to a digital multiply-and-accumulate output value according to the maximum reference voltage, the selected minimum reference voltage and the zone switch signal.

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