晶片間信號傳輸系統及晶片間電容耦合傳輸電路

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

102102997

專利證號

I 493666

專利獲證名稱

晶片間信號傳輸系統及晶片間電容耦合傳輸電路

專利所屬機關 (申請機關)

義守大學

獲證日期

2015/07/21

技術說明

三維積體電路3D-IC技術有眾多方法，如矽晶穿孔、電感耦合及電容耦合，其中以矽晶穿孔技術最受矚目。目前但矽晶穿孔缺點在於矽基板受鑽孔機械力影響而使得良率不高。使用非接觸式的電容耦合技術雖可以免除矽基板受鑽孔機械力之影響，但其測試方法目前無法使用傳統方法進行於三維積體電路3D-IC技術上探測。藉由應用雙端差動資料(Differential)信號，達到強化晶片之間的通信性能。我們提出之電路可以縮短晶片之間的距離使得通信品質大大改善，並達成自我測試之能力。 A number of interconnection technologies for integration of three-dimensional integrated circuits (3D-IC ) have been proposed, such as through silicon via, inductive coupling and capacitive coupling, ..etc. Among them the industry has been paid much attention to through silicon via technology. However, the drawbacks of through silicon via suffer from mechanical stress of silicon substrate, which seriously affects the production yield. Using non-contact capacitive coupling technology, it can provide the interconnection without the mechanical stress effects. However, the traditional test method for three-dimensional integrated circuits 3D-IC cannot apply to non-contact capacitive coupling circuits. Using double-end differential data signal with specific circuit topology, it not only can achieve communication between the dies but also can provide a self-test functionality.

備註

連絡單位 (專責單位/部門名稱)

產學智財營運總中心產學合作與專利技轉中心

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07-6577711ext2683

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