類神經網路系統、高密度內嵌式人工突觸元件及其操作方法

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

111108464

專利證號

I 802313

專利獲證名稱

類神經網路系統、高密度內嵌式人工突觸元件及其操作方法

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2023/05/11

技術說明

【中文】 本發明提供一種高密度內嵌式人工突觸元件，其包含半導體基板、選擇電晶體、金屬層以及記憶電晶體。選擇電晶體設置於半導體基板且包含第一閘極結構、汲極區及源極區。汲極區與源極區分別位於第一閘極結構之相對二側。金屬層連接汲極區。記憶電晶體設置於半導體基板並與選擇電晶體共平面。記憶電晶體包含第二閘極結構、第一電極區、第二電極區、第一憶阻器及第二憶阻器。第二閘極結構連接金屬層。第一憶阻器形成於第二閘極結構與第一電極區之間。第二憶阻器形成於第二閘極結構與第二電極區之間。藉此，達到雙位元的資料密度。 【英文】 The present disclosure provides a high density embedded-artificial synaptic element, which includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure, respectively. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and coplanar with the select transistor. The memory transistor includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region. Therefore, a data density of two bits is achieved.

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