時序設計變更的方法METHOD OF IMPLEMENTING TIMING ENGINEERING CHANGE ORDER

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

13/671,398

專利證號

US 8,776,000 B2

專利獲證名稱

時序設計變更的方法METHOD OF IMPLEMENTING TIMING ENGINEERING CHANGE ORDER

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2014/07/08

技術說明

一種利用路徑平滑化之時序設計變更的方法，首先將一電路的複數個時序違規路徑分解成複數個違規路徑區段。接著對各該違規路徑區段計算出一參數平滑曲線，且於該參數平滑曲線上產生複數個參考點。接著對各該違規路徑區段的各元件計算一可修性參數，該可修性參數與該元件及其對應之參考點之間的距離有關。接著根據各該元件的可修性參數對各該違規路徑區段選取至少一元件。接著為各該被選取的元件選取一備用元件，並將該備用元件配置於該被選取的元件所對應之違規路徑區段中。藉由該參數平滑曲線，元件的時序關鍵性能被較準確地判斷。 A method of implementing a timing engineering change order using smooth parametric curves includes the steps of: (a) decomposing a plurality of timing violating paths of a circuit into a plurality of violating path segments, each of which has gates; (b) computing a smooth parametric curve for each violating path segment and computing a plurality of reference points on each smooth parametric curve; (c) computing a fixability parameter for each gate of each violating path segment wherein the fixability parameter is related to the distance between a corresponding one of the gates and a corresponding one of the reference points corresponding to the gate; (d) choosing at least one gate for each violating path segment according the fixability parameter of each gate; and (e) choosing a spare cell for each chosen gate and disposing the chosen spare cell into the violating path segment of the chosen gate.

備註

本部(收文號1100065219)同意該校110年10月27日陽明交大研產學字第1100036963號函申請終止維護專利(陽明交大)

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