發明
中華民國
100120717
I 455138
非揮發性半導體記憶體裝置
國立交通大學
2014/10/01
本發明提供一種非揮發性半導體記憶體裝置,具有共用背閘極的獨立雙閘極SONOS記憶胞陣列的非揮發性記憶體結構,可應用於三維積成的快閃記憶體上。進一步地,各SONOS元件間可以無接面(junction-free)的形式串接而成。此種結構由於獨立雙閘極的控制,具有改善短通道效應、高寫入或抹移除效率,及有效避免讀取干擾等操作特性上的優點,藉由共用背閘極以及無接面的特性,可大幅簡化製程。此外,可以3D堆疊的方式,製作多層的記憶體元件,以增進晶片儲存密度。 This invention discloses a nonvolatile memory cell array which contains at least a string of SONOS cells with an independent double-gate (IDG) configuration. One of the double gates in one of the cells in the string with a storage ONO gate dielectric is isolated from the gates of other cells. The other gate in one of the cells in the string with an oxide gate dielectric is common and shared with other cells in the string. Such a scheme can retain the inherent merits associated with the IDG configuration, such as good control over the short-channel effects, improved P/E efficiency, and suppressed read disturb. Furthermore, the implementation of the common back-gate and junction-free features can greatly simplify the device fabrication, and thus advancing the feasibility of poly-Si NW devices for 3D nonvolatile memory manufacturing.
本部(收文號1100065219)同意該校110年10月27日陽明交大研產學字第1100036963號函申請終止維護專利(陽明交大)
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