MEMORY CELL FOR COMPUTING-IN-MEMORY APPLICATIONS,MEMORY UNIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

16/409,892

專利證號

US 10,636,481 B1

專利獲證名稱

MEMORY CELL FOR COMPUTING-IN-MEMORY APPLICATIONS,MEMORY UNIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2020/04/28

技術說明

運用於非揮發性運算系統之使用電阻式記憶體之非揮發性邏輯電路開發與探索 　　According to one aspect of the present disclosure, a memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell for the computing-in-memory applications includes a plurality of read-decoupled cells. The read-decoupled cells are connected to the first bit line, the second bit line, the word line and the read word line. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor is connected to the first read-decoupled transistor and the read word line. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells. According to another aspect of the present disclosure, a memory unit for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value, and the memory unit for the computing-in-memory applications includes a plurality of memory cells arranged in matrix. Each of the memory cells is one of an even-row memory cell and an odd-row memory cell. The even-row memory cell is located in an even row. The odd-row memory cell is located in an odd row, and each of the memory cells includes a plurality of read-decoupled cells. The read-decoupled cells are connected to the first bit line, the second bit line, the word line and the read word line. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor is connected to the first read-decoupled transistor and the read word line. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. In each of the memory cells, the second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells. According to further another aspect of the present disclosure, a computing method of the memory unit for the computing-in-memory applications provides a voltage level applying step and a computing step. The voltage level applying step is for applying a plurality of voltage levels to the first bit line, the second bit line, the word line, the read word line and the weight, respectively. The computing step is for driving each of the read-decoupled cells of the memory cells of the memory unit to generate the read bit line signal according to the voltage levels of the input value, the weight and the second transistor width

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