MULTI-BIT COMPUTING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

16/049,799

專利證號

US 10,381,071 B1

專利獲證名稱

MULTI-BIT COMPUTING CIRCUIT FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2019/08/13

技術說明

運用於非揮發性運算系統之使用電阻式記憶體之非揮發性邏輯電路開發與探索 According to one aspect of the present disclosure, a multi-bit computing circuit for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and an input port. The input port transmits an input value, and the multi-bit computing circuit for the computing-in-memory applications includes a memory cell array and a capacitor sharing unit. The memory cell array includes a plurality of memory cells connected to the first bit line, the second bit line, the word line and the input port. The memory cells store a weight which is formed in two's complement. Each of the memory cells generates a cell output signal according to the input value and the weight. The capacitor sharing unit is electrically connected to the memory cell array, and the capacitor sharing unit includes a plurality of switches, a plurality of capacitors and a sense amplifier. The switches are electrically connected to the cell output signals, respectively. The capacitors are electrically connected to the switches, respectively. The sense amplifier is electrically connected to the capacitors and generates a total operational value. The capacitors are located among the switches and the sense amplifier, and the switches are switched to enable the total operational value to be equal to the input value multiplied by the weight. According to another aspect of the present disclosure, a multi-bit computing circuit for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a plurality of input ports. Each of the input ports transmits an input value, and the multi-bit computing circuit for the computing-in-memory applications includes a memory cell array and a capacitor sharing unit. The memory cell array includes a plurality of memory cells arranged in a matrix and connected to the first bit line, the second bit line, the word line and the input ports. The memory cells store a plurality of weights which are formed in two's complement. Each of the memory cells generates a cell output signal according to one of the input values and one of the weights. The capacitor sharing unit is electrically connected to the memory cell array, and the capacitor sharing unit includes a plurality of switches, a plurality of capacitors and a sense amplifier. The switches are electrically connected to the cell output signals, respectively. The capacitors are electrically connected to the switches, respectively. The sense amplifier is electrically connected to the capacitors and generates a total operational value. The capacitors are located among the switches and the sense amplifier. The switches are switched to generate a plurality of multiply results by the input values respectively multiplied by the weights, and then the total operational value is equal to a sum of the multiply results. According to further another aspect of the present disclosure, a computing method of the multi-bit computing circuit for the computing-in-memory applications provides a voltage level applying step, a first computing step and a second computing step. The voltage level applying step is for applying a plurality of voltage levels to the input value, the weight and the switches, respectively. The first computing step is for driving the memory cells of the memory cell array to generate the cell output signal according to the voltage levels of the input value and the weight. The second computing step is for driving the capacitor sharing unit and switching the switches to enable the total operational value to be equal to the input value multiplied by the weight.

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