MEMORY UNIT WITH MULTI-BIT INPUT LOCAL COMPUTING CELL FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS, MEMORY ARRAY STRUCTURE WITH MULTI-BIT INPUT LOCAL COMPUTING CELL FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMP

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

17/082,000

專利證號

US 11,507,275

專利獲證名稱

MEMORY UNIT WITH MULTI-BIT INPUT LOCAL COMPUTING CELL FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS, MEMORY ARRAY STRUCTURE WITH MULTI-BIT INPUT LOCAL COMPUTING CELL FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMP

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2022/11/22

技術說明

MEMORY UNIT FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS BASED ON CHARGE SHARING, MEMORY ARRAY STRUCTURE FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS BASED ON CHARGE SHARING AND COMPUTING METHOD THEREOF: A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.

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