矽穿孔自我繞線電路及其繞線方法THROUGH-SILICON VIA SELF-ROUTING CIRCUIT AND ROUTING METHOD THEREOF

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

13/845,059

專利證號

US 8,754,704 B2

專利獲證名稱

矽穿孔自我繞線電路及其繞線方法THROUGH-SILICON VIA SELF-ROUTING CIRCUIT AND ROUTING METHOD THEREOF

專利所屬機關 (申請機關)

國立彰化師範大學

獲證日期

2014/06/17

技術說明

本發明提供一種矽穿孔自我繞線電路，其包含複數矽穿孔及複數平面晶片層。複數平面晶片層藉由矽穿孔連接，各平面晶片層包含一內建自我測試電路、一內建自我繞線交換網路及一核心電路。內建自我繞線交換網路連接內建自我測試電路。內建自我繞線交換網路包含複數有效位元引線及複數矽穿孔引線，矽穿孔引線對應矽穿孔。核心電路具有連接內建自我繞線交換網路之複數輸出入引線。本發明藉由內建自我測試電路測試矽穿孔，並經內建自我繞線交換網路路由矽穿孔並連結核心電路。 The present invention provides a through-silicon via self-routing circuit. The through-silicon via self-routing circuit comprises a plurality of through-silicon vias and a plurality of planner chip layers. The planners chip layers are connected to each other by the TSVs. Each planner chip layer comprises a built-in self-test circuit, a built-in self-routing network and a core circuit. The built-in self-routing network is connected to the built-in self-test circuit. The built-in self-routing network comprises a plurality of valid bit leads and plural through-silicon via leads, the plural through-silicon via leads corresponds to the plural through-silicon vias. The core circuit includes plural input-output leads. As a result, the redundant TSVs can be selected and chosen to be connected to the core circuit through built-in self-routing network.

備註

本部(收文號1100059213)同意該校110年9月27日研發字第1100400583號函申請終止維護專利(彰師大)

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