具有故障和軟錯誤容忍力的延遲鎖定迴路的電子裝置

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

109135135

專利證號

I 761984

專利獲證名稱

具有故障和軟錯誤容忍力的延遲鎖定迴路的電子裝置

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2022/04/21

技術說明

【中文】一電子裝置包括三個延遲鎖定迴路、三個虛擬表決電路，以及一表決電路。每一延遲鎖定迴路具有一第一輸入端、一第二輸入端及一輸出端，用以維持從第一輸入端所接收的一參考時脈訊號與從輸出端所輸出的一中間時脈訊號之間的一相位差。每一虛擬表決電路連接於每一延遲鎖定迴路的第二輸入端及輸出端之間，用以將中間時脈訊號的相位延遲相位差。表決電路從每一延遲鎖定迴路接收中間時脈訊號，並且依據來自每一延遲鎖定迴路的中間時脈訊號的邏輯準位，輸出一輸出時脈訊號。相位差補償由該中間時脈訊號穿過表決電路所造成的相位延遲，使得輸出時脈訊號同步於參考時脈訊號。 【英文】An electronic device includes three delay-locked loops, three dummy voter circuits, and a voter circuit. Each of the three delay-locked loops has a first input end, a second input end, an output end to maintain the phase difference between a reference clock signal received from the first input end and an intermediate clock signal output from the output end. Each of the three dummy voter circuits is connected between the second input end and the output end of each of the three delay-locked loops to delay the phase of the intermediate clock signal by the phase difference. The voter circuit receives the intermediate clock signal from each of the three delay-locked loops, and outputs an output clock signal according to the logic of the intermediate clock signal from each of the three delay-locked loops. The phase difference compensates for the phase delay of the intermediate clock signal passing through the voter circuit.

備註

連絡單位 (專責單位/部門名稱)

智財技轉組

連絡電話

03-5715131-62219

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