0.18um製程中強健靜電防護之用具NMOS開關整合矽控整流器之雙極電晶體電路

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

100132371

專利證號

I 517346

專利獲證名稱

0.18um製程中強健靜電防護之用具NMOS開關整合矽控整流器之雙極電晶體電路

專利所屬機關 (申請機關)

健行學校財團法人健行科技大學

獲證日期

2016/01/11

技術說明

一種0.18um製程中用於強健靜電防護具NMOS開關整合矽控整流器之雙極電晶體電路，其係在會產生燒損之線路上串接有一矽控整流器結合雙極電晶體，其特徵在於該矽控整流器結合雙極電晶體之陽極並接一N型金氧半電晶體，或並接一具電阻電容(RC)閘極耦合之N型金氧半電晶體;當靜電激增時，N型金氧半電晶體導通，降低線路之保持電壓不致燒損，正常直流通電時，N型金氧半電晶體關閉，使矽控整流器整合雙極電晶體不易進入鎖定當機狀態，該等裝置之保持電壓較傳統作為靜電防護矽控整流器提升了16倍◦ In 0.18μm CMOS process, A traditional SCR used for ESD protection is easily susceptible into latch-up and leads to circuit fail due to very low DC holding voltage (VH) performance of the SCR. Therefore, this work develops new circuit structures in a 0.18μm CMOS process for further improving holding voltage and latch-up Immunity. This circuit integrates an SCR-incorporated BJT with either a single NMOS or RC-gate-coupled NMOS structure. During ESD zapping, the NMOS can be regarded as a switch in turn-on state to clamp ESD voltage and reduce the holding voltage to enable SCR action, while the NMOS is switched off to disable the SCR action during DC standby condition.

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