時間至數位轉換器及數位控制時脈產生器及全數位時脈產生器TIME-TO-DIGITAL CONVERTER AND DIGITAL-CONTROLLED CLOCK GENERATOR AND ALL-DIGITAL CLOCK GENERATOR

專利類型

發明

專利國別 (專利申請國家)

美國

專利申請案號

13/570,104

專利證號

US 8,686,756 B2

專利獲證名稱

時間至數位轉換器及數位控制時脈產生器及全數位時脈產生器TIME-TO-DIGITAL CONVERTER AND DIGITAL-CONTROLLED CLOCK GENERATOR AND ALL-DIGITAL CLOCK GENERATOR

專利所屬機關 (申請機關)

國立交通大學

獲證日期

2014/04/01

技術說明

SSCG由clock re-generator、time-to-digital converter (TDC)、Divider、Encoder、semi-synchronous clocker (SSC)、Counter等模組所構成。clock re-generator產生長度為一個reference clock cycle之pulse，以避免reference clock之duty cycle不平衡之問題。接著TDC將reference clock period量化，此時TDC所量測到之reference clock period為duty cycle-free。TDC量化完成的資料經由Divider，並依據倍頻係數N產生近似1/N倍量化值，其中Divider電路以shifter方式實作，因此N為2的冪次方倍。Encoder再將此量化值對應至SSC控制訊號，最後由SSC產生相對應之時脈。SSC產生時脈後，Counter即開始計數，當SSC產生的cycle數達到N，SSC便停止產生時脈。而當下一個reference clock正緣觸發時，SSC便會開始產生時脈，Counter亦重新開始計數。使用m個SSC，可產生m個不同頻率的時脈，供系統中不同clock domain使用。 The proposed SSCG is composed of clock re-generator、time-to-digital converter (TDC)、Divider、Encoder、semi-synchronous clocker (SSC) and Counter. The clock re-generator generates a pulse which length is the same as a reference clock period to let TDC measure the period of reference clock with duty-cycle free. The TDC is used to measure the period of reference clock. After TDC, the Divider divides the TDC output valute by N. This Divider is implemented via a shifter (N is power of 2). Then the Encoder maps such period into a SSC control word, and the SSC can generate clock. When the SSC begins to generate an Nf -time high-speed clock, the Counter begins to count at each rising edge of SSC clock. The SSC generates clock until the cycle counts of SSC clock equals to N. When the next rising edge of reference clock comes, SSC begins to generate clock again. Based on this architecture, SSCG can generate m difference clocks by using m SSCs for difference clock domains in system.

備註

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