三維電阻式記憶體結構

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

112107919

專利證號

I 806812

專利獲證名稱

三維電阻式記憶體結構

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2023/06/21

技術說明

【中文】 本發明提供一種三維電阻式記憶體結構包含基底層、第一層、第二層、第三層及第四層。第一層包含二第一導電層及第一通孔。第二層包含三第二導電層及二第二通孔，其中一第二通孔及此三第二導電層之其中二者之間形成二第一電阻性元件，此三第二導電層之其中二者沿第一方向延伸。第三層包含三第三導電層及二第三通孔，其中一第三通孔及此三第三導電層之其中二者之間形成二第二電阻性元件，此三第三導電層之其中二者沿第二方向延伸。第四層包含第四導電層，第四導電層電性連接二第三通孔。第一方向垂直第二方向。藉此，提升記憶體的設置密度。 【英文】 A three-dimensional resistive random access memory structure is proposed. The three-dimensional resistive random access memory structure includes a base layer, a first layer, a second layer, a third layer and a fourth layer. The first layer includes two first conductive layers and a first via. One of the two first conductive layers is electrically connected to the base layer and the first via. The second layer includes three second conductive layers and two second vias, two first resistive elements are formed between one of the second vias and two of the second conductive layers. Another one of the second conductive layers is connected between the first via and another second via. Two of the second conductive layers are extended along a first direction. The third layer includes three third conductive layers and two third vias. Two second resistive elements are formed between one of the third vias and two of the third conductive layers. Another of the third conductive layers is connected between another second via and another third via. Two of the third conductive layers are extended along a second direction. The fourth layer includes a fourth conductive layer, and the fourth conductive layer is connected to two of the third vias. The first direction is vertical to the second direction. Thus, the disposed density of the three-dimensional resistive random access memory structure of the present disclosure can be increased.

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