寄生接面場效電晶體阻抗的降低方法

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

111117126

專利證號

I 804303

專利獲證名稱

寄生接面場效電晶體阻抗的降低方法

專利所屬機關 (申請機關)

國立陽明交通大學

獲證日期

2023/06/01

技術說明

一種寄生接面場效電晶體阻抗的降低方法，適於具有一半導體基底層之高功率元件，該降低方法包括：於該半導體基底層的頂表面設置複數個硬遮罩，其中，每一個硬遮罩係具有一下底面與一傾斜側壁，該傾斜側壁與下底面之間係形成有一銳角。之後，進行一基體離子植入製程，使相鄰的二該硬遮罩間形成有一基體區，該基體區係具有一上平面與一下平面，且該上平面之寬度係大於該下平面之寬度。緣此，本發明可控制寄生接面場效電晶體區具有下寬上窄的結構特徵，從而降低其阻抗，同時，因基體區底部角度的增加，亦有效地提升了該高功率元件的崩潰電壓。 A method for reducing parasitic junction field effect transistor resistance is provided. The disclosed method is applicable to a high power device having a semiconductor substrate layer, and includes the following steps: providing a plurality of hard masks on a top surface of the semiconductor substrate layer, wherein each hard mask has a bottom plane and a tilt sidewall such that an acute angle is formed there in between. A body ion implantation process is subsequently performed, such that a body region is formed between two adjacent hard masks. The body region has an upper surface and a lower surface, and a width of the upper surface is greater than that of the lower surface. Therefore, the present invention achieves to control a parasitic JFET region characterized by having a wider bottom and a narrower top, thereby reducing its resistance thereof. Meanwhile, since a bottom angle of the body region is increased, breakdown voltage of the high power device is increased as well.