延遲量測電路及其量測方法DELAY MEASUREMENT CIRCUIT AND MEASURING METHOD THEREOF

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

105116063

專利證號

I 585427

專利獲證名稱

延遲量測電路及其量測方法DELAY MEASUREMENT CIRCUIT AND MEASURING METHOD THEREOF

專利所屬機關 (申請機關)

國立中央大學

獲證日期

2017/06/01

技術說明

本發明系有關一種內建延遲量測技術，提供一種量測晶粒間訊號連接線之傳遞延遲的方法。為了能夠提高晶粒間訊號連接線延遲時間的量測精準度，且可以選定特定測試向量。我們提出一個內建延遲量測電路架構，予以直接量測晶粒間訊號連接線之延遲時間。該方法之電路架構包含延遲量測單元、參考用之晶粒間訊號連接線以及切換盒。本發明亦提出可有效低面積成本高解析度之延遲量測單元電路。基於此架構的延遲量測單元，可以讓多個晶粒間訊號連接線共用，使內建延遲量測技術的面積付出能夠更小。此外，本方法所採用的延遲量測流程可以消除兩晶粒間訊號連接線之間的連接線延遲。 A built-in self-measurement scheme is provided, which is applicable to measure the propagation delay of inter-die signal interconnections. To increase the measurement accuracy of the propagation delay of inter-die interconnection, and choose the specific test vector, we proposed the built-in self-measurement circuit architecture, which can measure the propagation delay of inter-die interconnections directly. The circuit of proposed scheme comprises delay measurement element, reference inter-die interconnections, and a plurality of switch boxes coupled to a plurality of inter-die signal interconnections. A low area cost, high resolution delay circuit of the delay measurement unit is proposed. The area overhead of the proposed method can be minimized, which the circuit of the delay measurement unit can be shared by multiple inter-die interconnections. Furthermore, a measurement flow of the proposed method can eliminate the delay of interconnection between two inter-die interconnections.

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