發明
中華民國
102118636
I 497721
增強型氮化鎵電晶體及其形成方法Enhanced GaN Transistor and the Forming Method Thereof
國立交通大學
2015/08/21
本發明揭露製作具高輸出電流之增強式氮化鎵電晶體之技術。我們利用InxAl1-xN /AlN之異質接面結構取代傳統之AlGaN/GaN異質接面結構並且於最上層成長p型InxAl1-xN層使之形成P-N接面,可製作出高輸出電流之增強型氮化鎵電晶體。而閘極漏電流也可因鈍化層的加入而降低,得以改善電晶體特性。此技術有助於減少元件待機時之功率損耗、降低元件應用至電路之複雜度,以及提升使空乏式與增強式整合之氮化鎵數位邏輯電路之可行性。 In this patent, we propose a technique of fabricating the enhancement mode GaN based transistor with high output drain current. This technique is achieved by using InxAl1-xN /AlN heterostructures and growth p- InxAl1-xN on the top layer in order to form PN semiconductor junction, which can fabricate enhance mode GaN transistor with high output current. However the gate leakage current would be decrease by adding passivation layer, it can improve the characteristic of transistor. The proposed device can improve the output current to achieve goals of low power consumption under off state of transistors, low complexity of circuit when applying the proposed devices, and possible integration of depletion mode and enhance mode of GaN transistors for GaN digital logic circuits.
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