溝槽式閘極功率金氧半場效電晶體之閘極製程方法及其形成之溝槽式閘極結構

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

111136331

專利證號

I 810076

專利獲證名稱

溝槽式閘極功率金氧半場效電晶體之閘極製程方法及其形成之溝槽式閘極結構

專利所屬機關 (申請機關)

國立陽明交通大學

獲證日期

2023/07/21

技術說明

【中文】一種溝槽式閘極功率金氧半場效電晶體之閘極製程方法及其形成之溝槽式閘極結構，其係提供一電晶體結構，並利用微影蝕刻定義溝槽區域。沿著溝槽沉積閘極氧化層後，形成其中具有間隔的二複晶矽側壁。利用濕蝕刻將複晶矽側壁底下的閘極氧化層去除，以在溝槽底部形成空缺區域。之後，通過氧化複晶矽側壁，形成厚氧化層，使其包覆複晶矽側壁外圍並填充溝槽底部的空缺區域。經厚氧化層包覆的複晶矽側壁之間可選擇性地具有間隔，使溝槽選擇性地被填滿。本發明可有效增加閘極底部的氧化層厚度、降低溝槽轉角曲率、並達到降低閘極-汲極電容之功效。【英文】 A gate fabrication method of an UMOSFET and a trench gate structure formed thereof are provided, comprising providing a transistor structure and a lithography process is employed to define a trench region therein. A gate oxide layer is deposited along the trench and two polysilicon sidewalls having a spacing there in between are formed afterwards. A wet etching process is used to remove the gate oxide layer underneath the polysilicon sidewalls such that a vacancy is formed at the bottom of the trench. By oxidizing the polysilicon sidewalls, a thick oxide layer is formed, compassing the periphery of the polysilicon sidewalls and filling the vacancy. The spacing can be alternatively remain between the two polysilicon sidewalls covered with the thick oxide layer, such that the trench can be alternatively filled. As a result, the present invention is effective in increasing an oxide thickness of the gate bottom, reducing the trench corner curvature as well as the parasitic gate-drain capacitance.