浮閘記憶體

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

106139282

專利證號

I 656625

專利獲證名稱

浮閘記憶體

專利所屬機關 (申請機關)

長庚大學

獲證日期

2019/04/11

技術說明

傳統快閃式記憶體利用閘極施加偏壓，吸引基板電子往閘極方向注入並儲存至浮閘內，然而，閘極和浮閘之間夾著一層阻擋氧化層，使得閘極電壓必須乘以耦合率才能等效成浮閘的電位，考量到記憶體的可靠度，阻擋氧化層需要足夠厚度以避免電子漏失，因此，耦合率會被阻擋氧化層的電容值限制住而無法提升，我們提出一種概念目的是為了提升耦合率，在浮閘和基板之間的穿隧氧化層，利用具有負電容特性的鐵電材料取代傳統高介電係數材料，在元件操作過程中，使得耦合率的值趨近於一，浮閘所感應的電位和施加於閘極的偏壓幾乎相同，此外，資料讀取時的次臨界擺幅也會因為負電容的特性而突破傳統統電晶體的極限，同時改善記憶體操作速度和功率消耗，達到高密度記憶體的目標。 In conventional flash memory, electrons were attracted by the positive bias at gate electrode and stored in the floating gate. There is a coupling ratio of the memory, which is resulted from a blocking layer between gate electrode and floating gate. Considering the reliability of memory, the thickness of blocking layer should be thick enough to prevent the electrons from leakage. Therefore, the coupling ratio would be limited by the capacitance of blocking oxide. In this patent, we propose a concept to use the ferroelectric material with a negative capacitance as the tunneling layer between the floating gate and substrate. It can make the coupling ratio approach one and lead to the floating gate potential close to the gate bias in the memory operation. In addition, the subthreshold swing could overcome the limit of traditional transistor because of the negative capacitance. We can improve both operation speed and power consumption to achieve the high-density memory.

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